View BD9411F_8994823.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

product structure silicon monolithic integrated circuit this product has not designed protection against radioactive rays . 1 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 tsz22111 ? 14 ? 001 www.rohm.com led drivers for lcd backlights 1ch boost up typ e white led driver for large lcd bd9411 f general description bd9411 f is a high efficiency driver for white leds and is designed for large lcds. bd9411 f has a boost dcdc converter that employs an array of le ds as the light source. bd9411 f has some protect functions against fault conditions, such as over - voltage protection (ovp), over current limit protection of dcdc (ocp), led ocp protection , and o v er - boost protection (fbmax) . therefore it is available for t he fail - safe design over a wide range output voltage. features ? dcdc converter with current mode ? led protection circuit ( over boost protection, led ocp protection) ? over - voltage protection (o vp) for the output voltage v out ? adjustable soft start ? adjustable oscillation frequency of dcdc ? wide range of analog dimming 0.2v to 3.0v ? uvlo detection for the input voltage of the power stage ? led dimming pwm over duty protection (odp) applications ? tv, computer display, lcd backlighting key specification s ? operating p ower supply voltage range : 9.0v to 35.0v ? oscillator frequency of dcdc : 150khz (rt=100k ) ? operating current : 3.3 ma ( typ ) ? operating temperature range : - 40 c to +10 5 c package (s) w(typ) x d(typ) x h(max) sop18 1 1.20mm x 7.80m m x 2.01mm pin pitch 1.27mm figure 1 . sop18 typical application circuit figure 2 . typical application circuit v out stb reg 90 rt pwm ss adim fail rs dutyp dutyon ovp dimout gate isens e cs vcc v in fb v cc gnd uvlo
2 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f pin con fig uration (s) figure 3. pin configuration pin description ( s ) no. terminal name function 1 vcc power supply pin 2 stb ic o n /off pin 3 ovp over voltage protection detection pin 4 uvlo under voltage lock out detection pin 5 ss soft start se tting pin 6 dutyon over duty protection on/off pin 7 pwm external pwm dimming signal input pi n 8 fail error detection output pin 9 adim adim signal input pin 10 rt dc/dc switching frequency setting pin 11 dutyp over duty protection setting pin 12 fb error amplifier output pin 13 isense led c urrent detection input pin 14 gnd - 15 dimout dimming signal output for n mos 16 gate dc/dc switching output pin 17 cs dc/dc output current detect pin , ocp input pin 18 reg 90 9.0 v output voltage pin vcc 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 1 stb ovp uvlo ss dutyon pwm fail reg 90 cs gate dimout gnd isense fb dutyp 9 adim 10 rt
3 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f block diagram (s) figure 4 . block diagram auto - restart control ovp dimout vreg gate isense cs rt pwm vcc reg 90 gnd + - - control logic reg 90 v in vcc uvlo tsd reg 90 uvlo current sense osc ss pwm comp - + + error amp ledocp overboost 1 . 015 v fb ss - fb clamper v cc package : sop 18 reg 90 adim rs ss stb 1 / 3 uvlo uvlo leb 1 m ovp fail detect fail dutyp osc over duty protection dutyon 1 m 1 m
4 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f absolute maximum ratings (tj =25 c ) parameter symbol rating unit power supply voltage v cc - 0.3 to + 36 v ss, rt, isense, fb, cs, dutyp pin v oltage ss, rt, isense, fb, cs, dutyp - 0.3 to + 7 v reg90, dimout, gate pin v oltage reg90, dimout, gate - 0.3 to + 13 v ovp, uvlo, pwm, adim , stb , fail , dutyon pin v oltage ovp, uvlo, pwm, adim , stb , fail , dutyon - 0.3 to + 20 v operating temperature range topr - 40 to +105 c junction temp erature tjmax 150 c storage t emperature r ange tstg - 55 to +150 c thermal resistance ( note 1) parameter symbol thermal resistance (typ) unit 1s ( note 3 ) 2s2p ( note 4) sop18 junction to ambient j a 179.3 119.9 c /w junction to top characterization parameter ( note 2 ) jt 20.0 17.0 c /w (note 1) based on jesd 51 - 2a(still - air) (note 2) the thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface of the component package. (note 3) using a pcb board based on jesd 51 - 3. (note 4) using a pcb board based on jesd 51 - 7. layer number of measurement board material board size single fr - 4 114.3mm x 76.2mm x 1.57mmt top copper pattern thickness footprints and t races 70 m layer number of measurement board material board size 4 layers fr - 4 114.3mm x 76.2mm x 1.6mmt top 2 internal layers bottom copper pattern thickness copper pattern thickness copper pattern thickness footprints and traces 70 m 74.2mm x 74.2mm 35 m 7 4.2mm x 74.2mm 70 m recommended operating ranges parameter symbol range unit power supply voltage vcc 9.0 to 35 .0 v dc/dc oscillation frequency fsw 50 to 10 00 khz effective range of adim signal vadim 0.2 to 3. 0 v pwm input frequency fpwm 90 to 2000 hz
5 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f el ectrical characteristics ( unless otherwise specified v cc = 24 v t j =25 c ) parameter symbol min typ max unit conditions total current consumption circuit current i cc 3.3 6.6 ma v stb =3 .0 v, pwm= 3.0 v circuit current (standby) i st 40 80 a v stb =0 v uvlo block operation voltage v cc v uvlo_vcc 6.5 7.5 8.5 v v cc =sweep up hysteresis voltage v cc v uhys_vcc 150 300 600 mv v cc =sweep down uvlo release voltage v uvlo 2.88 3.00 3.12 v v uvlo =sweep up uvlo hysteresis voltage v uhys 250 300 350 mv v uvlo =sw eep down uvlo pin leak current i v uvlo_lk - 2 0 2 a v uvlo =4 .0 v dc/dc block isense threshold voltage 1 v led1 0.225 0.233 0.242 v v adim = 0.7v isense threshold voltage 2 v led2 0.656 0.667 0.677 v v adim = 2.0v isense threshold voltage 3 v led3 0.988 1.000 1. 012 v v adim = 3.0 v isense c lamp v oltage v led4 0.990 1.015 1.040 v v adim = 3.3 v ( as masking analog dimming ) oscillation frequency f ct 142.5 150 157.5 k hz rt=100k rt s hort p rotection r ange v rt _det - 0.3 - v rt 90% v rt =sweep down rt t erminal v oltage v rt 1.6 2.0 2.4 v rt=100k gate pin max duty output d max_duty 90 95 99 % rt=100k gate pin on resistance (as source) r on _g so 2.5 5.0 10.0 gate pin on resistance (as sink) r on _g si 2.0 4.0 8.0 ss pin source current i ssso - 3.75 - 3.0 - 2.25 a v ss =2.0v ss pi n on resistance at off r ss_l - 3.0 5.0 k soft start ended voltage v ss_end 3. 52 3.70 3.88 v ss=sweep up dc/dc block fb source current i fbso - 1 15 - 100 - 85 a v isense =0.2v, v adim = 3 .0v, v fb =1.0v fb sink current i fbsi 85 100 1 15 a v isense =2.0v, v adim = 3 .0v, v fb =1.0v dc/dc protection block ocp detect voltage 1 v cs 1 360 400 440 mv cs=sweep up , pulse by pulse ocp detect voltage 2 v cs 2 0.85 1.00 1.15 v cs=sweep up ovp detect voltage v ovp 2.88 3.00 3.12 v v ovp sweep up ovp detect hysteresis v ovp_hys 1 50 200 250 mv v ovp sweep down ovp pin leak current i ovp_lk - 2 0 2 a v ovp =4 .0 v , v stb =3.0v led protection block led ocp detect voltage v ledocp 2.88 3.0 0 3.12 v v isense =sweep up over b oost d etection v oltage v fbh 3.84 4.00 4.16 v v fb =swe ep up dimming block adim pin leak current i ladim - 2 0 2 a v adim = 2.0 v isense pin leak current i l_isense - 2 0 2 a v isense =4 .0 v dimout source on resistance r on _dim so 5.0 10.0 20.0 dimout sink on resistance r on _dim si 4.0 8.0 16.0 reg 90 block reg 90 output voltage 1 v reg90_1 8.91 9.00 9.09 v i o =0ma reg 90 output voltage 2 v reg90_2 8.865 9.00 9.135 v i o = - 15ma reg 90 available current | i reg90 | 15 - - ma reg 90 _uvlo detect voltage v reg90_th 5.22 6.0 0 6.78 v v reg90 =sweep down, v stb =0v reg 90 discharge resistance v reg90_ dis 13.2 22.0 30.8 k stb=on - >off, v reg90 =8.0v, pwm=l
6 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f electrical characteristics ( unless otherwise specified v cc = 24 v t j =25 c ) parameter symbol min typ max unit conditions stbh 2. 0 - 18 v stb pin low voltage v stbl - 0.3 - 0.8 v stb pull down resistance r stb 60 0 1000 1400 k stb =3.0v pwm_h 1.5 - 18 v pwm pin low voltage v pwm_l - 0.3 - 0.8 v pwm pin pull down resistance r pwm 60 0 1000 1400 k pwm =3.0v dtyon_h 1.5 - 18 v dutyon pin low voltage v dtyon_l - 0.3 - 0.8 v dutyon pin pull down resistance r dtyon 60 0 1000 1400 k dutyon =3.0v od p - 35 - % f pwm =120hz , duty p=341 k dtyp _det - 0.3 - v dutyp 90% v dutyp =sweep down dutyp t erminal v oltage v dtyp 1.6 2.0 2.4 v dutyp=100k cp - 20 - ms f ct =800khz auto timer t auto - 163 - ms f ct =800khz fail l 0.25 0.5 1.0 v i fail =1ma
7 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f typical performance curves (reference data) figure 5 . operating circuit current figure 6 . standby circuit current figure 7 . duty cycle vs fb character figure 8 . isense f eedback voltage vs adim character stb=3 .0 v pwm=3 .0v ta=25 c stb=0v pwm=0v ta=25 c vcc=24v ta=25 c v cc =24v ta=25 c stb=3 .0 v pwm=3 .0v ta=25 c v cc =24v ta=25 c 0 10 20 30 40 50 60 70 80 10 15 20 25 30 35 v cc [v] i stb [ua] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10 15 20 25 30 35 v cc [v] i cc [ma] 0 20 40 60 80 100 0 1 2 3 4 v fb [v] duty cycle[%] 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 1 2 3 4 v adim [v] isense feecback voltage[v]
8 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f pin descriptions this is the power supply pin of the ic. input range is from 9 v to 35 v. the operation starts at more than 7. 5 v ( t yp) and shuts down at less tha n 7.2 v ( t yp) . pin 2 : stb this is the on/off setting terminal of the ic. at startup, internal bias starts at high level , and then pwm dcdc boost starts after pwm rise edge inputs. note: ic status (ic on/off) transits depending on the voltage inputted to st b terminal. a void the use of inte rmediate level (from 0.8v to 2.0 v). pin 3 : ovp the ovp terminal is the input for over - voltage protection . if ovp is more than 3.0v ( t yp) , the over - voltage protection (ovp) will work. at the moment of these detections, it s et s gate=l, dimout=l and starts to count up the abnormal interval . if ovp detection continued to count four gate clocks, ic 's operation will be stop. ( please refer to "ovp detection" timing chart on page26 ) the ovp pin is high impedance, because the intern al resistance is not connected to a certain bias. even if ovp function is not used, pin bias is still required because the open connection of this pin is not a fixed potential . the setting example is separately described in the ovp setting " section on pag e16 . pin 4 : uvlo u nder v oltage l ock o ut pin is the input voltage of the power stage. , ic starts the boost operation if uvlo is more than 3 . 0 v ( t yp) and stops if lower than 2. 7 v ( t yp). the uvlo pin is high impedance, because the internal resistance is not connected to a certain bias. even if uvlo function is not used, pin bias is still required because the open connection of this pin is not a fixed potential. the setting example is sepa rately described in the uvlo setting " section on page15 pin 5 : ss th is is the pin which sets the s oft start interval of dc/dc converter . i t performs the constant current charge of 3 .0 a ( t yp ) to external capacitance css . the switching duty of gate output will be limited during 0 v to 3.7 v ( typ ) of the ss voltage . so the soft start interval tss can be expressed as follows c ss : the external capacitance of the ss pin . the logic of ss pin asserts low is defined as the dc/dc operation stop state after protection function or pwm is not input high level after stb reset release. when ss capacitance is under 1nf, take note if the in - rush current during startup is too large , or if over boost detection (fbmax ) mas k timing is too short. please refer to soft start behavior in the tim ing chart " section on page 13 . pin 6 : dutyon this is the on/off setting terminal of the led pwm over duty protection (odp). by adjusting dutyon input voltage, it is on/off of the odp adjusted. state dutyon input voltage odp=o n dutyon= - 0.3v to + 0.8 v odp=off dutyon= 1.5v to 1 8 . 0v this is the pwm dimming signal input terminal. the high / low level of pwm pins are the following. state pwm input voltage pwm=h pwm= 1.5v to 18. 0 v pwm=l pwm= \ + 0.8v pin 8 : fail this is fail signal output (open drain) pin. a t normal operation, nmos will be in on (500 ohm typ ) state , during abnormality detection nmos will be in open state (off) . [sec] 10 23 . 1 6 ss ss c t ? ? ?
9 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f pin 9 : adim this is the input pin for analog dimming signal. the isense feedback point is set as 1/3 of this pin bias. if more than 3.0v ( typ ) is input, isense feedback voltage is clamped to limit to flow led large current. in this condition, the input current is caused. please refer to terminal explanation. pin 10 : rt this is the dc/dc switching frequency setting pin . dcdc frequency is decided by connected resistor. (ideal) the oscillation setting ranges from 50khz to 1 0 00k h z. the setting example is sep arately described in the dcdc oscillation frequency se tting section on page15 pin 1 1: dutyp this is the odp setting pin. the odp (over duty protection) is the function to limit duty of led pwm frequency f pwm by odp detection duty (odp duty ) set by resistance (r duty ) connected to dutyp pin. relationship bet ween led pwm frequency f pwm , odp detection duty and dutyp resistance (ideal) the r dutyp setting ranges from 15 k to 1m . the setting example is sepa rately described in the odp setting section on page16. this is the output terminal of error amplifier. fb pin rises with the same slope as the ss pin during the soft - start period. after soft - start completion (ss>3.7v ( t yp) ), it operates as follows. when pwm=h, it detects isense terminal voltage and outputs error signal compared to analog dimming signal (adim). when pwm=l, ic holds the ovp voltage at the edge of pwm=h to l, and operates to hold the adjacent voltage. please refer to timing chart section it detects over boost (fbmax) over fb=4.0v( typ ). after the ss completion, if fb>4.0v a nd pwm=h continues 4clk gate, the cp counter starts. after that, only the fb>4.0v is monitored, when cp counter reaches 16384clk ( 2 14 clk ) , ic 's operation will be stop . ( please refer to timing chart section on page27 . ) the loop compensation setting is de scribed in section "loop compensation" on page21 . pin 1 3 : isense this is the input terminal for the current detection. error amplifier compares isense voltage and the lower voltage between 1/3 of the adim (analog dimming terminal) voltage and 1.015 v ( t yp) for fb voltage control. and this terminal detects abnormal led 's over - current when isense voltage continues over 3.0v ( t yp) during 4 clks (equivalent to 40us at f osc = 100khz), dc/dc operation becomes stop . (please refer to timing chart section on page 28 .) figure 9 . relationship of the fee dback voltage and adim figure 1 0 . isense terminal circuit example pin 1 4 : gnd this is the gnd pin of the ic . - + 1 . 015 v v out isense fb error amp + dimout bd 941 1 1 / 3 adim rs ] [ ] [ [%] 1172 ? ? ? k hz f odp r pwm duty dutyp adim [ v ] 0 3 . 0 1 . 0 v gain = 1 / 3 0 . 2 error amp vth [ v ] 67 mv 1 . 015 v ] [ ] [ 15000 ? ? k khz f r sw rt
10 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f v o u t isense dimout reg 90 r dim bd 941 1 pin 15 : dimout this is the output pin for external dimming nmos. the table below shows the rough output logic of each operation state, and the output h level is reg 90 . please refer to timing chart section fo r detailed explanations, because dimout logic has an exceptional behavior. please insert the resist or r dim between the dimming mos gate to improve the over shoot of led current, as pwm turns from low to high. status dimout output normal s ame logic to p wm abnormal gnd level pin 16 : gate this is the output terminal for driving the gate of the boost mosfet. the high level is reg90 . frequency can be set by the resistor connected to rt. r efer to pin description for the frequency setting. pin 1 7 : cs the cs pin has two fun ctions. 1. dc / dc current mode feedback terminal the inductor current is converted to the cs pin voltage by the sense resistor r cs. this voltage compared to the voltage set by error amplifier controls the output pulse . 2. inductor current limit (ocp) te rminal the cs terminal also has an over current protection (ocp). if the voltage is more than 0.4v ( t yp) , the switching operation will be stopped compulsorily. and the next boost pulse will be restarted to normal frequency. in addition, the cs voltage is m ore than 1.0v(t yp) during 4clks gate operation, ic operation will be stop . as above ocp operation, if the current continues to flow nevertheless gate=l because of the destruction of the boost mos, ic will stops the operation completely. both of the above functions are enabled after 300ns ( t yp) when gate pin asserts high , because the leading edge blanking function (leb) is included into this ic to prevent the effect of noise. please refer t o ocp setting / calculation method for the current rating of dcdc p arts section on page18 , for detailed explanation . if t he capacitance c cs in the right f igure is increased to a micro order, please be careful that the limited value of nmos drain current id is more than the simple calculation. because the current id flows not only through r cs but also through c cs , as the cs pin voltage moves according to id. pin 18 : reg90 this is the 9.0 v( t yp) output pin . available current is 15 ma (min). the characteristic of v cc line regulation at reg90 is shown as figure. v cc must be used in more than 10.5v for stable 9v output. please place the ceramic capacitor connected to reg90 pin (1.0 f to 10 f) closest to reg90 - gnd pin. figure 1 1 . dimout terminal circuit example figure 1 2 . cs terminal circuit example figure 1 3 . reg90 line regulation v in cs gnd bd 941 1 gate r cs c cs id 0 2 4 6 8 10 0 5 10 15 20 25 30 35 v cc [v] v reg90 [v]
11 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f list of the protection function d etection c ondition ( t yp c ondition) protect f unction detection p in detect c ondition release c ondition timer o peration protection typ e detection c ondition pwm ss fbmax fb fb > 4.0v h( 4 clk) ss> 3.7 v fb < 4.0v 2 14 clk immediately auto - r estart after detection (judge periodically whether normal or not) led ocp isense isense > 3.0v - - isense < 3.0v 4clk immediately auto - r estart after detection (judge periodically wh ether normal or not) rt gnd short rt rt 5v - - release rt =high no r estart by release uvlo uvlo uvlo<2.7v - - uvlo>3.0v no r estart by release reg 90 uvlo reg 90 reg 90 < 6.0 v - - reg 90 > 6.5 v no r estart by release vcc uvlo vcc vcc< 7.2 v - - vcc>7. 5 v no r estart by release ovp ovp ovp>3.0v - - ovp<2. 8 v 4clk immediately auto - r estart after detection (judge periodically whether normal or not) ocp cs cs>0.4v - - - no pulse by p ulse ocp detection2 c s cs> 1.0 v - - cs <1.0 v 4clk immediately auto - r estart after detection (judge periodically whether normal or not) dutyp gnd short dutyp dutyp 5v - - release dutyp =high no r estart by release odp (*1) pwm dutyon=h and pwm on d uty > s etting d uty by dutyp r esistor h - - no cycle by c ycle to reset the fbmax, led ocp, ovp and ocp detection2 protection , please set stb logic to l once. otherwise the detection of vccuvlo, reg90 uv lo is required. the clock number of timer operation corresponds to the boost pulse clock. (*1) w hen pwm duty count start, pwm=h l is input, when pwm=l h is input, the odp is reset. the gate output, the dimout output maintain l until pwm=h l is input in pwm = 100% again when odp works once. list of t he p rotect ion f unction o peration protect f u nction operation of the p rotect f unction dc/dc gate o utput dimming t ransistor (dimout) l ogic ss p in fail pin fbmax stop after timer operation l ow after timer operation d ischarge after timer operation high after timer operation led ocp stop immediately i mmediately high , l ow after timer operation discharge after timer operation high after timer operation rt gnd short stop immediately immediately low not discharge low rt high short stop immediately immediately low not discharge low stb stop immediately l ow after reg90 uvlo detects d ischarge immediately low uvlo stop immediately immediately low discharge immediately low reg90 uvlo stop immediately immediately low discharge immediately low vcc uvlo stop immediately immediately low discharge immediately low ovp stop immediately immediately low d ischarge after timer operation l ow ocp stop immediately normal operation not discharge low ocp detection2 stop after timer operation l ow after timer operation d ischarge after timer operation high aft er timer ope ration dutyp gnd short stop immediately immediately low not discharge low dutyp high short stop immediately immediately low not discharge low odp immediately low immediately low not discharge low please refer to timing chart section for details .
12 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f app lication c ircuit e xample introduce an example application using the bd9411 f. ? b asic a pplication e xample figure 1 4 . b asic application example ? a nalog d imming or pwm d imming examples figure 1 5 . example circuit for analog di mming figure 1 6 . example circuit for pwm dimming rs stb reg 90 rt pwm ss adim fail v out dutyp dutyon ovp dimout gate isense cs vcc v in fb v cc gnd uvlo adim rs reg 90 pwm open dutyp dutyon fail ovp dimout gate isense cs vcc v in fb v cc gnd uvlo stb reg 90 rt ss v out stb reg 90 rt pwm ss adim rs reg 90 dutyp dutyon fail ovp dimout gate isense cs vcc v in fb v cc gnd uvlo v out
13 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f external c omponents s election 1. start up operation and s oft s tart external capacitance setting the below explanation is the start up sequence of this ic figure 17 . startup waveform figure 18 . c ircuit behavior at startup explanation of start up sequence 1. reference voltage re g90 starts by stb=h . 2. s s starts to charge at the tim e of first pwm=h. at this moment, t he ss voltage of slow - start starts to equal fb voltage , and the circuit becomes fb=ss regardless of pwm logic. 3. when fb=ss reaches the lower point of internal sawtooth waveform, gate terminal outputs pulse and starts to boost vout. 4 . it boosts vout and vout reaches the voltage to be able to flow led current. 5 . if led current flows over decided level, fb=ss circuit disconnects and startup behavior completes. 6 . then it works normal operation by feedback of isense terminal . if led current doesn't flow when ss becomes over 3.7v ( typ ) , ss=ff ci rcuit completes forcibly and fbmax protection starts. method of setting ss external capacitance according to the sequence described above, start time tss that startup completes with fb=ss condition is the time that fb voltage reaches the feedback point. the capacit ance of ss terminal is defined as css and the feedback voltage of fb terminal is defined as vfb . the equality on t fb is as follows. if css is set to a very small value, ru s h current flows into the inductor at startup. on the contrary, if c ss is enlarged too much, led will light up gradually. since css differs in the constant set up with the characteristic searched for and differs also by factors, such as a voltage rise ratio, an output capacitance, dcdc frequency, and led current, please c onfirm with the system. setting example when css=0.1uf , iss=3 a ,and startup completes at vfb=3.7v , ss setting time is as follows . [sec] 123 . 0 ] a [ 10 3 ] v [ 7 . 3 ] f [ 10 1 . 0 t 6 6 ss ? ? ? ? ? ? ? l e d _ o k s s = f b c i r c u i t s s f b 5 v o s c d r i v e r c o m p g a t e d i m o u t v o u t i l e d p w m p w m = l : s t o p 3 u a c s s i s e n s e c s s t b s s s l o p e p w m g a t e v o u t i l e d l e d _ o k f b o s c 2 1 3 4 5 6 [sec] ] a [ 3 ] v [ vfb ] f [ c t ss ss ? ?
14 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 2. vcc s eries r esistance setting h ere are the following effects of inserting series resistor rvcc into v cc line . (i) in order to drop the voltage v cc , it is possible to suppress the heat generation of the ic. (ii) it can limit the inflow current to v cc line. however, if resistance r vcc is set bigger, v cc voltage becomes under minimum operation voltage (v cc <9v). rvcc mus t be set to an appropriate series resistance . ic s inflow current line i_in has the following inflow line s . ? ic s circuit current i cc ? c urrent of r reg connected to reg90 i reg ? c urrent to drive fet s gate i _gate the se decide the voltage v at r vcc . vcc terminal voltage at that time can be expressed as follows. here, judgement is the 9v minimum operation volta ge. please consider a sufficient margin when setting the series resistor of v cc . setting example above equation is translated as follows. when v in =24v , i cc =2.0ma , r reg =10k and i dcdc =2ma , r v cc s value is calculated as follow s . (i cc is 3.3 ma( t yp) ) . please set each values with tolerance and margin. 3. led current setting led current can be adjusted by setting the resistance r s [ ] which connect s to isense pin and adim [v] . relationship between r s and i led current with dc dimming (adim<3.0 v) without dc dimming (adim>3.0v) setting example if i led current is 2 00ma and adim is 2 .0v, we can calculate r s as below . figure 19 . vcc series resistance circuit example f igure 2 0 . led current setting example - + 1 . 015 v v out isense fb error amp + dimout bd 941 1 1 / 3 adim rs vcc vin rvcc v i _ in reg 90 + - rreg ireg dcdc driver gate i _ gate internal block icc idcdc ? ? ] [ 9 ] [ ] [ ] [ ] [ ] [ v r a i a i a i v vin v v vcc reg dcdc cc cc ? ? ? ? ? ? ] [ ] [ ] [ ] [ 9 ] [ ] [ a i a i a i v v vin r reg dcdc cc vcc ? ? ? ? ? ] [ 26 . 3 ] [ 10000 / ] [ 8 . 5 ] [ 002 . 0 ] [ 002 . 0 ] [ 9 ] [ 24 ] [ ? ? ? ? ? ? ? ? k v a a v v r vcc ] [ ] [ ] [ 3 1 ? ? ? a i v adim r led s ] [ ] [ ] [ 015 . 1 ? ? a i v r led s ] [ 33 . 3 ] [ 2 . 0 ] [ 0 . 2 3 1 ] [ ] [ 3 1 ? ? ? ? ? ? a v a i v adim r led s
15 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 4. d cdc oscillation frequency setting r rt which connects to rt pin sets the oscillation frequency f sw of dcdc . sw and rt resistance (ideal) setting example when dcdc frequency fsw is set to 200khz, r rt is as follow s . 5. uvlo setting u nder v oltage l ock o ut pin is the input voltage of the power stage. ic starts boost operation if uvlo is more than 3 . 0 v ( t yp) and stops if lower than 2. 7 v ( t yp). the uvlo pin is high impedance, because the internal resistance is not connected to a certain bias. so, the bias by the external components is required , because the open connecti on of this pin is not a fixed potential. d etection voltage is set by divid ing resistors r1 and r2 . the resistor values can be calculated by the formula below. uvlo detection equa tion as v in decreases, r1 and r2 values are set in the following formula by the vin det that uvlo detect s. uvlo release equa tion r1 and r2 setting is decided by the equation above. the equation of uvlo release voltage is as follow s. setting example if the normal input voltage, v in is 24v, the detect voltage of uvlo is 18v, r2 is 30k, r1 is calculated as follows. by using these r1 and r2, the release voltage of uvlo, vin can , can be calculated too as follows. figure 2 1 . rt terminal setting example figure 22 . uvlo settin g example ] k [ ] v [ 7 . 2 ]) v [ 7 . 2 ] v [ vin ( ] k [ 2 r 1 r det ? ? ? r t r r t g a t e c s g n d r c s f r e q u e n c y ( f s w ) u v l o c u v l o v i n r 1 + - o n / o f f 2 . 7 v / 3 . 0 v r 2 ] [ ] [ 15000 ? ? k khz f r sw rt ] [ 75 ] [ 200 15000 ] [ 15000 ? ? ? ? k khz khz f r sw rt ] [ 0 . 170 ] [ 7 . 2 ]) [ 7 . 2 ] [ 18 ( ] [ 30 ] [ 7 . 2 ]) [ 7 . 2 ] [ ( ] [ 2 1 ? ? ? ? ? ? ? ? ? ? k v v v k v v v vin k r r det ] [ 0 . 20 ] [ ] [ 30 ] [ 30 ] [ 170 ] [ 0 . 3 ] [ 2 ]) [ 2 ] [ 1 ( ] [ 0 . 3 v v k k k v k r k r k r v vin can ? ? ? ? ? ? ? ? ? ? ? ? ? ] v [ ] k [ 2 r ]) k [ 2 r ] k [ 1 r ( v 0 . 3 vin can ? ? ?
16 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 6. odp setting r dutyp which co nnects to odp pin sets the odp detection d uty . pwm , odp detection duty and dutyp resistance (ideal) setting example when led pwm frequency f pwm , is set to 120 hz and odp detec tion duty ( odp duty ) is set to 35% , r dutyp is as follow s . figure 2 4 . the gate and the dimout waveform as pwm dimming (odp) 7. ovp setting the ovp terminal is the input for over - voltage protection of output voltage . the ovp pin is high i mpedance, because the internal resistance is not connected to a certain bias. d etection voltage of v out is set by divid ing resistors r1 and r2 . the resistor values can be calculated by the formula below. ovp detection equa tion if v out is boosted abnormally, vovp det , the detect voltage of ovp, r1, r2 can be expressed by the following formula. ovp release equa tion by using r1 and r2 in the above equation, the release voltage of ovp, vovp can can be exp ressed as follows. setting example if the normal output voltage, v out is 40v, the detect voltage of ovp is 48v, r2 is 10k, r1 is calculated as follows. by using these r1 and r2, the release voltage of ovp, vovp can can be calculated as follow s. figure 25 . ovp setting example figure 23 . odp settin g example dutyp r dutyp gate cs r cs dimout isense gnd r s pwm ovp covp v out r2 r1 + - ovp 2.8v/3.0v ] [ ] [ 0 . 3 ]) [ 0 . 3 ] [ ( ] [ 2 1 ? ? ? ? ? k v v v vovp k r r det ] [ ] [ 2 ]) [ 2 ] [ 1 ( 8 . 2 v k r k r k r v vovp can ? ? ? ? ? ? ] [ 150 ] [ 3 ]) [ 3 ] [ 48 ( ] [ 10 ] [ 0 . 3 ]) [ 0 . 3 ] [ ( ] [ 2 1 ? ? ? ? ? ? ? ? ? ? k v v v k v v v vovp k r r det ] [ 8 . 44 ] [ ] [ 10 ] [ 150 ] [ 10 ] [ 8 . 2 ] [ 2 ]) [ 2 ] [ 1 ( ] [ 8 . 2 v v k k k v k r k r k r v vovp can ? ? ? ? ? ? ? ? ? ? ? ? ? ] [ 8 . 341 ] [ 120 [%] 35 1172 ? ? ? ? k hz r dutyp ] [ ] [ [%] 1172 ? ? ? k hz f odp r pwm duty dutyp pwm gate dimout f pwm odp duty
17 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 8. protection timer (cp counter) setting, auto - restart timer setting about over boost protection (fbmax) , protection timer (cp counter) is set by counting the clock frequency which is set at the rt pin. about the behavior from abnormal detection for use timer , please refer to the t iming c hart section . the condition fb>4.0v(t yp) and pwm=h contin ues more than four gate clocks, counting starts from the timing. after that, fbmax protection monitor only the fb voltage and dcdc operation will be stop after below time has passed. here, timer time = time until ic's operation stop , auto time = auto restart timer s time r rt = resistor value connected to rt pin protection timer time when rt=100kohm ] [ 10 5 . 1 ] [ 131072 10 5 . 1 2 7 10 17 s k r r auto rt rt time ? ? ? ? ? ? ? ] [ 2 . 109 10 5 . 1 ] [ 100 16384 10 5 . 1 ] [ 16384 7 7 ms k k r timer rt time ? ? ? ? ? ? ? ? ? ] [ 8 . 873 10 5 . 1 ] [ 100 131072 10 5 . 1 ] [ 131072 7 7 ms k k r auto rt time ? ? ? ? ? ? ? ? ? ] [ 10 5 . 1 ] [ 16384 10 5 . 1 2 7 10 14 s k r r timer rt rt time ? ? ? ? ? ? ?
18 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f dcdc p arts s e lection 1. ocp setting / calculation method for the current rating of dcdc parts ocp detect ion stops the switching when the cs pin voltage is more than 0.4v ( t yp) . the resistor value of cs pin, r cs needs to be considered by the coil l current. and the curre nt rating of dcdc external parts is required more than the peak current of the coil. shown below are the calculation method of the coil peak current, the selection method of r cs (the resistor value of cs pin) and the current rating of the external dcdc par ts at continuous current mode . the calculation method of the coil peak current, i peak at continuous current mode at first, since the ripple voltage at cs pin depends on the application condition of dcdc, the following variables are used. vout voltage =v out [v] led total current =i out [a] dcdc input voltage of the power stage =v in [v] efficiency of dcdc = [%] and then, the average input current iin is calculated by the following equation. and the ripple current of the inductor l (i l [a]) can be calculat ed by using dcdc the switching frequency, f sw , as follows. on the other hand, the peak current of the inductor i peak can be expressed as follows. (1) therefore, the bottom of the ripple current i min is or 0 if imin>0, the o peration mode is ccm (continuous current mode), otherwise the mode is dcm (discontinuous current mode). ( the selection method of rcs at continuous current mode ) ipeak flows into r cs and that causes the voltage signal to cs pin. (please refer to the timing chart at the right) peak voltage vcs peak is as follows. as this vcspeak reaches 0.4v ( t yp) , the dcdc output stops the switching. therefore, r cs value is necessary to meet the condition below. (the current rating of the external dcdc parts) the peak current as the cs voltage reaches ocp level (0.4v ( t yp) ) is defined as i peak_det . (2) the relationship among i peak (equation (1)), i peak_det (equation (2)) and the current rating of parts is required to meet the following plea se make the selection of the external parts such as fet, inductor, diode meet the above condition. the current rating of parts figure 26 . coil current waveform v in v out gate cs gnd r cs il l fsw i out ] [ ] [ ] [ 4 . 0 det _ a r v i cs peak ? ? i i n a ) ( t ) 0 . 4 v ( t ) v ) ( v ) v c s [ v ] i l [ a ] i l ( t ) n [ v ] i p e a k i m i n v c s p e a k ] [ [%] ] [ ] [ ] [ a v v a i v v i in out out in ? ? ? ? ] [ ] [ ] [ ] [ ] [ ]) [ ] [ ( a hz f v v h l v v v v v v i sw out in in out l ? ? ? ? ? ] [ 2 ] [ ] [ a a i a i i l in peak ? ? ? ] [ v i r vcs peak cs peak ? ? ?? ?? det _ peak peak i i 2 ] [ ] [ min a i a i i l in ? ? ? ] [ 4 . 0 ] [ v v i r peak cs ?? ?
19 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f [ setting example ] output voltage = v out [v] = 40v led total current = i out [a] = 0.48v dcdc input voltage of the power stage = v in [v] = 24v efficiency of dcdc = [%] = 90% averaged input current iin is calculated as follows. if the switching frequency, f sw = 200khz, and the inductor, l=100 h, the ripple current of the inductor l (il[a]) can be calculated as follows. therefore the inductor peak c urrent, i peak is if rcs is assumed to be 0.3 r cs value confirmation the above condition is met. and i peak_det , the current ocp works, is if the current rating of the used parts is 2a, this inequality meets the above relationship. the parts selection is proper. and i min , the bottom of the il ripple current, can be calculated as follows. t his inequality implies that the operation is continuous current mode. calculation result of the peak current current rating confirmation ] [ 0 . 2 ] [ 33 . 1 ] [ 13 . 1 a a a ?? ?? ? ] [ 89 . 0 [%] 90 ] [ 24 ] [ 48 . 0 ] [ 40 [%] ] [ ] [ ] [ ] [ a v a v v v a i v v a i in out out in ? ? ? ? ? ? ? ? ] [ 48 . 0 ] [ 10 200 ] [ 40 ] [ 10 100 ] [ 24 ]) [ 24 ] [ 40 ( ] [ ] [ ] [ ] [ ]) [ ] [ ( 3 6 a hz v h v v v hz f v v h l v v v v v v i sw out in in out l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ] [ 13 . 1 2 ] [ 48 . 0 ] [ 89 . 0 ] [ 2 ] [ ] [ a a a a a il a i i in peak ? ? ? ? ? ? 0 ] [ 65 . 0 ] [ 48 . 0 ] [ 13 . 1 ] [ 2 ] [ ] [ ?? ? ? ? ? ? ? a a a a a i a i i l in min ?? ?? det _ peak peak i i v v a ipeak rcs vcs peak 4 . 0 ] [ 339 . 0 ] [ 13 . 1 ] [ 3 . 0 ?? ? ? ? ? ? ? ] [ 33 . 1 ] [ 3 . 0 ] [ 4 . 0 det _ a v i peak ? ? ?
20 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 2. inductor selection the inductor value affects the input ripple cu rrent , as shown the "ocp setting" on page18 . where l: coil inductance [h] v out : dcdc output voltage [v] v in : input voltage [v] i out : output load current (the summation of led current) [a] i in : input current [a] f sw : oscillation frequenc y [hz] in continuous current mode, S i l is set to 30% to 50% of the output load current in many cases. in using smaller inductor, the boost is operated by the discontinuous current mode in which the coil current returns to zero at every period. *the current exceeding the rated current value of inductor flown through the coil causes magnetic saturation, results in decreasing in efficiency. inductor needs to be selected to have such adequate margin that peak current does not exceed the rated current va lue of the inductor. *to reduce inductor loss and improve efficiency, inductor with low resistance components (dcr, acr) needs to be selected 3. output capacitance cout selection output capacitor needs to be selected in consideration of equivalent series resistance required to even the stable area of output voltage or ripple voltage. be aware that set led current may not be flown due to decrease in led terminal voltage if output ripple component is high. output ripple voltage S v out is determined by equat ion (4): when the coil current is charged to the output capacitor as mos turns off, much output ripple is caused. much ripple voltage of the output capacitor may cause the led current ripple. * rating of capacitor needs to be s elected to have adequate margin against output voltage. *to use an electrolytic capacitor, adequate margin against allowable current is also necessary. be aware that the led current is larger than the set value transitionally in case that led is provided w ith pwm dimming especially. 4. mosfet selection there is no problem if the absolute maximum rating is larger than the rated current of the inductor l, or is larger than the sum of the tolerance voltage of c out and the rectifying diode v f . the product wit h small gate capacitance (injected charge) needs to be selected to achieve high - speed switching. * one with over current protection setting or higher is recommended. * the selection of one with small on resistance results in high efficiency. 5. rectifyin g diode selection a schottky barrier diode which has current ability higher than the rated current of l, reverse voltage larger than the tolerance voltage of c out , and low forward voltage vf especially needs to be selected. figure 27. i nductor current waveform and diagram figure 28 . o utput capacitor diagram (4) ] [ ????? v r i v esr l out ? ? ] [ ] [ ] [ ] [ ] [ ]) [ ] [ ( a hz f v v h l v v v v v v i sw out in in out l ? ? ? ? ? ] [ 2 ] [ ] [ a a i a i ipeak l in ? ? ? ] [ [%] ] [ ] [ ] [ a v v a i v v i in out out in ? ? ? ? i l v o u t v i n c o u t r c s l i l v out v in c out r cs l r esr i l
21 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f loop compensation a current mo de dcdc converter has each one pole (phase lag) f p due to cr filter composed of the output capacitor and the output resistance (= led current) and zero (phase lead) f z by the output capacitor and the esr of the capacitor. moreover, a step - up dcdc converte r has rhp zero (right - half plane zero point) f zrhp which is unique with the boost converter. this zero may cause the unstable feedback. to avoid this by rhp zero, the loop compensation that the cross - over frequency f c, set as follows, is suggested. fc = f z rhp /5 (f zrhp : rhp zero frequency) considering the response speed, the calculated constant below is not always optimized completely. it needs to be adequately verified with an actual device. figure 29 . output stage and error amplifier diag ram i. calculate the pole frequency fp and the rhp zero frequency f zrhp of dc/dc converter where i led = the summation of led current, (continuous current mode) ii. calculate the phase compensation of the error amp output (f c = f zrhp /5 ) above equation is described for lighting led without the oscillation. the value may cause much error if the quick response for the abrupt change of dimming signal is required. to improve the transient response, r fb1 needs to be increased, and c fb1 needs to be decreased. it needs to be adequately verified with an actual device in consideration of variation from parts to parts since phase margin is decreased. + - c fb1 fb r fb1 gm v out i led c fb2 v o u t v i n c o u t r c s l r e s r ] [ 2 ) 1 ( 2 hz i l d v f led out zrhp ? ? ? ? ? ? ] [ ) 1 ( 5 1 ? ? ? ? ? ? ? ? ? d v gm f i r f r out p led cs zrhp fb ] [ 2 hz c v i f out out led p ? ? ? ? out in out v v v d ? ? ] [ 10 0 . 4 4 s gm ? ? ? ] [ 2 5 2 1 1 1 1 f f r f r c zrhp fb c fb fb ? ? ? ? ? ? ? ?
22 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f timing c hart 1. pwm start up 1 ( i nput pwm s ignal a fter i nput stb s ignal) figure 3 0 . pwm start up 1 ( i nput pwm s ignal a fter i nput stb s ignal) (*1) reg90 starts up when stb is changed from low to high . in the state where the pwm signal is not inputted, ss terminal is not charged and dcdc do es n t start to boost, either. (*2) when reg90 is more than 6.5 v ( t yp ) , the reset signal is released. (* 3 ) the charge of the pin ss starts at the positive edge of pwm=l to h, and the soft start starts. and while the ss is less than 0. 4 v, the pulse does not output. the pin ss continues ch arging in spite of the assertion of pwm or ovp level. (* 4 ) the soft start interval will end if the voltage o f the pin ss, v ss reaches 3.7 v ( t yp) . by this time, it boost s v out to the voltage where the set led current flows. the abnormal detection of fbmax st arts to be monitored. (* 5 ) as stb=l, the boost operation is stopped instantaneously. (discharge operation continues in the state of stb=l and reguvlo=l. please refer to the "turn off" section on page24 ) (* 6 ) in this diagram, before the charge period is com pleted, stb is changed to high again. as stb=h again , the boost operation restarts the next pwm=h. it is the same operation as the timing of (*2). ( for capacitance setting of ss terminal, please refer to the "method of setting ss external capacitance" sect ion on page13 . (note1) at fail terminal pull - up to external voltage, fail voltage is "h" until reg90 over 6.5v. (initial fail's nmos is "off" before ic's circuit will operate). vcc 7 . 5 v stb gate (* 2 ) (* 3 ) (* 4 ) (* 5 ) pwm reg 90 6 . 5 v ss 3 . 7 v off ss normal standby ss standby 0 . 4 v 0 . 4 v (* 1 ) (* 6 ) state fail (note1) (at pull - up external voltage)
23 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 2. pwm start up 2 ( i nput stb s ignal after i nputted pwm s ignal) figure 3 1 . pwm start up 2 ( i nput stb s ignal after i nputted pwm s ignal) (*1) reg90 starts up when stb=h. (*2) when reg90 uvlo releases or pwm is inputted to the edge of pwm= lh , ss charge starts and soft start period is started. and while the ss is less than 0. 4 v, the pulse does not output. the pin ss continues charging in spite of the assertion of pwm or ovp level. (*3) the soft start interval will end if the voltage of the pin ss, v ss reaches 3.7 v ( t yp) . by this time, it boosts v out to the point where the set led current flows. the abnormal detection of fbmax starts to be monitored. (*4) as stb=l, the boost operation is stopped instantaneously (gate=l, ss=l) . (discharge opera tion works in the state of stb=l and reg90 uvlo= h . please refer to the "turn off" section on page 24 ) (*5) in this diagram, before the dis charge period is completed, stb is changed to high again. as stb=h again, operation will be the same as the timing of (* 1). (note1) at fail terminal pull - up to external voltage, fail voltage is "h" until stb change from "l" to "h" . (initial fail's nmos is "off" before ic's circuit will operate). vcc stb gate reg 90 ss 3 . 7 v ss ss standby (* 1 ) (* 2 ) (* 3 ) (* 4 ) (* 5 ) normal pwm 0 . 4 v 0 . 4 v 7 . 5 v 6 . 5 v off state fail (note1) (at pull - up external voltage)
24 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 3. turn o f f figure 3 2 . turn o f f (*1) as st b= hl , boost operation stops and reg90 start s to discharge. the discharge curve is decided by reg90 discharge resistance an d the capacitor of the reg90 terminal . (*2) while stb=l, reg90 uvlo=h , dimout becomes same as pwm . when reg90 = 9.0 v is less than 6.0 v ( t yp ) , ic becomes off state. v out is discharged completely until this time . i t should be set to avoid a sudden brightness. (note1) at fail terminal pull - up to external voltage, fail voltage is "h" until stb change from "l" to "h". (initial fail's nmos is "of f" before ic's circuit will operate). reg 90 uvlo stb reg 90 6 . 0 v dimout gate vout ss on discha r ge off (* 1 ) (* 2 ) pwm fail (note1) (pull - up to external voltage) state
25 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 4. soft s tart f unction figure 3 3 . soft s tart f unction (*1) the ss pin charge does not start by just stb=h. pwm=h is required to start the soft start. in the low ss voltage, the gate pin duty depends on the ss voltage. and while the ss is less than 0. 4 v, the pulse does not output. (*2) by the time stb=l, the ss pin is discharged immediately. (*3) as the stb recovered to stb=h, the ss charge starts immediately by the logic pwm=h in th is chart. (*4) the ss pin is discharged immediately by the uvlo=l . (*5) the ss pin is discharged immediately by the vccuvlo=l . (*6) the ss pin is discharged immediately by the reg90 uvlo=l . (*7) the ss pin is not discharged by the abnormal detection for use timer typ e protection such as ovp until the timer finish . (note1) at fail terminal pull - up to external voltage, fail voltage is "h" until stb change from "l" to "h". (initial fail's nmos is "off" before ic's circuit will operate). stb 3 . 0 v 2 . 8 v pwm ovp ss 2 . 7 v 3 . 0 v 7 . 2 v 7 . 5 v uvlo vccuvlo reg 90 uvlo (* 1 ) (* 2 ) (* 3 ) (* 4 ) (* 5 ) (* 6 ) (* 7 ) 6 . 0 v 6 . 5 v 4 clk f ail (note1) (at pull - up external voltage)
26 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 5. ovp d etection figure 3 4 . ovp d etection (*1) as ovp is detected, the output gate=l, dimout=l, and the abnormal counter starts . (*2) if ovp is released within 4 clocks of abnormal counter of the gate pin frequency, the boost operation restarts . (*3) as the ovp is detected again, the boost operation is stopped. (*4) as the ovp detection continues up to 4 count by the abnormal counter, ic 's operation will be stop . after ic operation stop , auto counter starts counting. (*5) once ic operation stop , the boost operation doesn't restart even if ovp is released. (*6) when auto counter reaches 131072clk ( 2 17 clk) , ic will be auto - restarted . the auto restart interval can be calculated by the external resistor of rt pin. (please refer to the " timer latch t ime setting, auto - restart timer setting " section on page17 . ) (*7) the operation of the ovp detection is not related to the logic of pwm. stb pwm 3 . 0 v 2 . 8 v 3 . 0 v 2 . 8 v 3 . 0 v 2 . 8 v abnormal counter ovp ss gate dimout start start reset end start reset less than gate 4 count gate 4 count less than gate 4 count normal ovp normal abnormal (* 1 ) (* 2 ) (* 3 ) (* 4 ) (* 5 ) normal ovp normal state ovp (* 6 ) (* 7 ) abnormal abnormal 0 . 4 v fail reg 90 auto counter start end 131072 count ic's operation stop and auto counter
27 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 6. fbmax d etection figure 3 5 . fbmax d etection (*2) during the soft start, it is no t judged to the abnormal state even if the fb=h(fb>4.0v ( t yp) ). (*3) when the pwm=h and fb=h, the abnormal counter doesnt start immediately. (*4) the cp counter will start if the pwm=h and the fb=h detection continues up to 4 clocks of the gate frequency. once the count starts, only fb level is monitored. (*5) when the fbm ax detection continues till the cp counter reaches 16384clk ( 2 14 clk) , ic 's operation will be stop . the operation stop interval can be calculated by the external resistor of rt pin. (please refer to the "timer latch time setting, auto - restart timer setting" section on page 17 . ) (*6) when auto counter reaches 131072clk ( 2 17 clk) , ic will be auto - restarted . the auto restart interval can be calculated by the external resistor of rt pin. (please refer to the "timer latch time setting, auto - restart timer setting" s e ction on page17 . ) (note1) at fail terminal pull - up to external voltage, fail voltage is "h" until stb change from "l" to "h". (initial fail's nmos is "off" before ic's circuit will operate). end start auto counter start end 131072 count 16384 count stb gate fb 4 . 0 v cp counter ss 3 . 7 v ss cp countor normal ss state standby ic's operation stop and auto counter ????? ????? (* 1 ) (* 2 ) (* 3 ) (* 4 ) (* 5 ) (* 6 ) pwm 4 . 0 v reg 90 fail (note1) (at pull - up external voltage)
28 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f 7. led ocp d etection figure 3 6 . led ocp d etection (*1)if isense>3.0v ( t yp) , ledocp is detected, and gate becomes l. to detect ledocp continuously, the dimout is compulsorily high, regardless of the pwm dimming signal. (*2)when the ledocp releases within 4 counts of the gate frequenc y, the boost operation restarts. (*3) as the ledocp is detected again, the boost operation is stopped. (*4)if the ledocp detection continues up to 4 counts of gate frequency. ic 's operation will be stop . after ic operation stop , auto counter starts count ing. (*5)once ic 's operation stop , the boost operation doesn't restart even if the ledocp releases. (*6) when auto counter reaches 131072clk ( 2 17 clk) , ic will be auto - restarted . the auto restart interval can be calculated by the external resistor of rt pi n. (please refer to the "timer latch time setting, auto - restart timer setting" section on page17 . ) (*7) the operation of the ledocp detection is not related to the logic of the pwm. stb 3 . 0 v abnormal counter isense ss gate dimout start start reset end start less than 4 count 4 count normal ledocp norma l abnormal (* 1 ) (* 2 ) (* 3 ) (* 4 ) (* 5 ) normal state (* 6 ) (* 7 ) abnormal abnormal ledocp ledocp pwm 0 . 4 v 3 . 0 v 3 . 0 v 3 . 0 v 3 . 0 v 3 . 0 v fail reg 90 auto counter start end less than 4 count reset normal ic's operation stop and auto counter 131072 count
29 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f i/o equivalent circuits ovp uvlo ss rt pwm dutyon adim fb dimout / reg90 gate / reg90 / cs stb isense dutyp fail 500 fail reg 90 gate gnd cs 100 k vcc s t b 1 m 1 0 0 k 5 v ovp 100 k 5 v i s e n s e 2 0 k 5 v u v l o 5 0 k 5 v dutyp s s 5 v 3 k rt p w m 1 m 1 0 0 k 5 v dutyon 1 m 100 k 5 v 2 0 k 5 v a d i m f b reg 90 dimout gnd 100 k vcc
30 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f operational notes 1. reverse c onnection of p ower s upply connecting the power supply in reverse polarity can damage the ic. take pr ecautions again st reverse polarity when connecting the power supply , such as mounting an external diode between the power supply and the ic s power supply pin s. 2. power s upply l ines design the pcb layout pattern to provide low impedance supply lines. furthermore, connect a capacitor to ground at all power supply pins . consider the effect of temperature and aging on the capacitance value when using electrolytic capacitors. 3. g round voltage ensure that no pins are at a voltage below that of the ground pin at any time, even du ring transient condition. 4. g round w iring p attern when using both small - signal and large - current ground traces, the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluct uations in the small - signal ground caused by large currents. also ensure that the ground traces of external components do not cause variations on the ground voltage. the ground lines must be as short and thick as possible to reduce line impedance. 5. thermal c onsideration should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the properties of the chip. in case of exceeding this absolute maximum rating, increase the board siz e and copper area to prevent exceeding the maximum junction t emperature rating. 6. recommended o perating c onditions these conditions represent a range within which the expected characteristics of the ic can be approximately obtained . the e lectrical character istics are guaranteed under the conditions of each parameter . 7. inrush current when power is first supplied to the ic, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence a nd delays, especially if the ic has more than one power supply. therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. operation u nder s trong e lectromagnetic f ield operating t he ic in the presence of a strong electromagnetic field may cause the ic to malfunction . 9. testing on a pplication b oards when testing the ic on an application board, connecting a capacitor directly to a low - impedance output pin may subject the ic to stress. always discharge capacitors completely after each process or step. the ics power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. to prevent damage from static discharge, gr ound the ic during assembly and use similar precautions during transport and storage. 10. inter - pin short and mounting errors ensure that the direction and position are correct when mounting the ic on the pcb. incorrect mounting may result in damaging the ic. avoid nearby pins being shorted to each other especially to ground , power supply and output pin . inter - pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins during assembly to name a few. 11. unused input pins input pins of an ic are often connected to the gate of a mos transistor. the gate has extremely high impedance and extremely low capacitance. if left unconnected, the electric field from the o utside can easily charge it. the small charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause unexpected operation of the ic. so unless otherwise specified, unused input pins should be conne cted to the power supply or ground line.
31 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f operational notes C continued 12. regarding the i nput p in of the ic this monolithic ic contains p+ isolation and p substrate layers between adjacent elements in order to keep them isolated. p - n junctions are formed at the intersection of the p layers with the n layers of other elements, creating a parasitic diode or transistor. for example (refer to figure below): when gnd > pin a and gnd > pin b, the p - n junction operates as a parasitic diode. when gnd > pin b, t he p - n junction operates as a parasitic transistor. parasitic diodes inevitably occur in the structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. therefore , condit ions that cause these diodes to operate, such as applying a voltage lower than the gnd voltage to an input pin (and thus to the p substrate) should be avoided. fig ure 37 . example of monolithic ic structure 13. ceramic capacitor when using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with temperature and the decrease in nominal capacitance due to dc bias and others. 14. area of safe operation (aso) operate the ic such that the output voltage, output current, and the maximum junction temperature rating are all within the area of safe operation (aso). 15. thermal shutdown circuit(tsd) this ic has a built - in thermal shutdown circuit that prevents heat damage to the ic. normal operation should always be within the ics maxim um junction temperature rating. if however the rating is exceeded for a continued period, the junction temperature (tj) will rise which will activate the tsd circuit that will turn off all output pins. when the tj falls below the tsd threshold, the circuit s are automatically restored to normal operation. note that the tsd circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no circumstances, should the tsd circuit be used in a set design or for any purpose other tha n protecting the ic from heat damage. 16. over c urrent p rotection c ircuit (ocp) this ic incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. this protection circuit is effective in preventing damage due to sud den and unexpected incidents. however, the ic should not be used in applications characterized by continuous operation or transitioning of the protection circuit. n n p + p n n p + p s u b s t r a t e g n d n p + n n p + n p p s u b s t r a t e g n d g n d p a r a s i t i c e l e m e n t s p i n a p i n a p i n b p i n b b c e p a r a s i t i c e l e m e n t s g n d p a r a s i t i c e l e m e n t s c b e t r a n s i s t o r ( n p n ) r e s i s t o r n r e g i o n c l o s e - b y p a r a s i t i c e l e m e n t s
32 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f ordering informatio n b d 9 4 1 1 f - e 2 part number package f:sop 18 packaging and forming specification e2: embossed tape and reel marking diagram s sop18(top view) b d 9 4 1 1 f part number marking lot number 1pin mark
33 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f physical dimension, tape and reel information package name sop18 (unit : mm) pkg : sop18 drawing no. : ex115 - 5001 (max 11.55 (include.burr))
34 / 34 tsz02201 - 0t2t0c100250 - 1 - 2 ? 20 17 rohm co., ltd. all rights reserved. 20.feb.2017 rev.001 www.rohm .com tsz22111 ? 15 ? 001 b d 9411f revision history date revision changes 20 . feb . 2 01 7 001 new release
notice - p ga - e rev.00 3 ? 201 5 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our p roducts are designed and manufactured for application in ordinary electronic equipment s ( such as av equipment, oa equipment, telecommunication equipment, home elec tronic appliances, amusement equipment, etc.). if you intend to use our products in devices requiring extremely high reliability ( such as medical equipment ( n ote 1 ) , transport equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, f uel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life , bodily injury or serious damage to property ( specific applications ) , please consult with the rohm sales represe ntative in advance. unless otherwise agreed in writing by rohm in advance, rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any rohm s products for specific appl ications. ( n ote1) m edical e quipment c lassification of the s pecific applications japan usa eu china class 2. rohm designs and manufactures its products subject to strict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsi bilities, adequate safety measures including but not limited to fail - safe design against the physical injury, damage to any property, which a failure or malfunction of our products may cause. the following are examples of safety measures: [a] installation of protection circuits or other protective devices to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our p roducts are designed and manufactured for use under standard conditions a nd not under any special or extraordinary environments or conditions, as exemplified below . accordingly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arising from the use of any rohms p roduct s under any special or extraordinary environments or conditions . if you intend to use our products under any special or extraordinary environments or conditions (as exemplified below), your independent v erification and confirmation of product performance, reliability, etc, pri or to use, must be necessary : [a] use of our products in any types of liquid, including water, oils, chemicals, and organic solvents [b] use of our products outdoors or in places where the p roducts are exposed to direct sunlight or dust [c] use of our prod ucts in places where the p roducts are exposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the p roducts are exposed to static electricity or electromagnetic waves [e] use of our products in p roximity to heat - producing components, plastic cords, or other flammable items [f] s ealing or coating our p roducts with resin or other coating materials [g] use of our products without cleaning residue of flux (even if you use no - clean type fluxes, cleanin g residue of flux is recommended); or washing our products by using water or water - soluble cleaning agents for cleaning residue after soldering [h] use of the p roducts in places subject to dew condensation 4 . the p roducts are not subject to radiation - proo f design . 5 . please verify and confirm characteristics of the final or mounted products in using the products. 6 . in particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied, confirmation of pe rformance characteristics after on - board mounting is strongly recommended. avoid applying power exceeding normal rated power; exceeding the power rating under steady - state loading condition may negatively affect product performance and reliability. 7 . de - rate power dissipation d epending on a mbient temperature . when used in sealed area, confirm that it is the use in the range that does not exceed the maximum junction temperature. 8 . confirm that operation temperature is within the specified range described in the product specification. 9 . rohm shall not be in any way responsible or liable for f ailure induced under devian t condition from what is defined in this document . precaution for mounting / circuit board design 1. when a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product performance and reliability. 2. in principle, the reflow soldering method must be used on a surface - mount products, the flow soldering method must be used on a through hole mount products. i f the flow soldering method is preferred on a surface - mount products , please consult with the roh m representative in advance. for details , please refer to rohm mounting specification
notice - p ga - e rev.00 3 ? 201 5 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, please allow a sufficient margin considerin g variations of the characteristics of the p roducts and external components, including transient characteristics, as well as static characteristics. 2. you agree that application notes, reference designs, and associated data and information contained in t his document are presented only as guidance for products use . therefore, in case you use such information, you are solely responsible for it and you must exercise your own independent verification and judgment in the use of such information contained in t his document. rohm shall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such information. precaution for electrostatic this p roduct is e lectrostatic sensitive product, which may be damaged due to e lectrostatic discharge. please take proper caution in your manufacturing process and stor age so that voltage exceeding the product s maximum rating will not be applied to p roducts. please take special care under dry condition (e .g. grounding of human body / equipment / solder iron, isolation from charged objects, setting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriorate if the p roducts are stored in the places where : [a] the p roducts are exposed to sea winds or corrosive gases, including cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to direct sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage condition, solderability of products out of recommended storage time period may be degraded. it is strongly recommended to confirm solderability before using p roducts of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the correct direction, which is indicated on a carton with a symbol. otherwise bent leads may occur due to excess ive stress applied when dropping of a carton. 4. use p roducts within the specified time after opening a humidity barrier bag. baking is required before using p roducts of which storage time is exceeding the recommended storage time period . precaution for p roduct l abel a two - dimensional barcode printed on rohm p roduct s label is for rohm s internal use only . precaution for d isposition when disposing p roducts please dispose them properly using a n authorized industry waste company. precaution for foreign e xchange and foreign t rade act since concerned goods might be fallen under listed items of export control prescribed by foreign exchange and foreign trade act, please consult with rohm in case of export. precaution regarding intellectual property rights 1. all information an d data including but not limited to application example contained in this document is for reference only. rohm does not warrant that foregoing information or data will not infringe any intellectual property rights or any other rights of any third party reg arding such information or data. 2. rohm shall not have any obligations where the claims, actions or demands arising from the combination of the products with other articles such as components, circuits, systems or external equipment (including software). 3. no license, expressly or implied, is granted hereby under any intellectual property rights or other rights of rohm or any third parties with respect to the products or the information contained in this document. provided, however, that rohm will not assert it s intellectual property rights or other rights against you or your customers to the extent necessary to manufacture or sell products containing the products, subject to the terms and conditions herein. other precaution 1. this document may not be reprinted or reproduced, in whole or in part, without prior written consent of rohm. 2. the products may not be disassemble d, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. i n no event shall you use in any way whatso ever the products and the related technical information contained in the products or this document for any military purposes , including but not limited to, the development of mass - destruction weapons . 4. the proper names of companies or products described in this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties.
datasheet datasheet notice ? we rev.001 ? 2015 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information.
datasheet part number BD9411F package sop18 unit quantity 2000 minimum package quantity 2000 packing type taping constitution materials list inquiry rohs yes BD9411F - web page distribution inventory

▲Up To Search▲

Price & Availability of BD9411F

	To Download BD9411F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .